LTC3608_技术文档

LTC3613

24V, 15A Monolithic

Step Down Regulator with

Differential Output Sensing

DESCRIPTION

The LTC^®3613 is a monolithic synchronous step-down

switching regulator capable of regulating outputs from 0.6V

to5.5Vwithupto15Aoutputcurrent.Thecontrolledon-time

constantfrequencyvalleycurrentmodearchitectureallowsfor

bothfasttransientresponseandconstantfrequencyswitch-

FEATURES

n

Wide V Range: 4.5V to 24V;

IN

V

OUT

Range: 0.6V to 5.5V at up to 15A

0.67% Output Voltage Accuracy

n

Controlled On-Time Valley Current Mode Architecture,

Excellent Current Sharing Capability

Frequency Programmable from 200kHz to 1MHz

and Synchronizable to External Clock

n

ing in steady-state operation, independent of V , V

and

IN OUT

load. This also provides excellent current sharing capability.

R

or Inductor DCR Current Sensing With

SENSE

Differential output voltage sensing along with a precision

internal reference combine to offer 0.6ꢀ7 output regula-

tion, even if the output ground reference deviates from

local ground by 500mV. The switching frequency can be

programmedfrom200kHzto1MHzwithanexternalresis-

tor. The switching frequency is also phase synchronizable

to an external clock in applications where switching noise/

EMI reduction is crucial.

Accurate Current Limit

n

Fast Transient Response

Differential Output Voltage Sensing Allowing 500mV

Common Mode Remote Ground

n

t

= 65ns; t

= 105ns

ON(MIN)

OFF(MIN)

Overvoltage Protection and Current Limit Foldback

Power Good Output Voltage Monitor

Voltage Tracking Start-Up

Verylowt andt timesallowfornear07andnear1007

External V Input for Bypassing Internal LDO

Micropower Shutdown: I = 15μA

ꢀmm × 9mm 56-pin QFN Package

ON

OFF

CC

duty cycles, respectively. Voltage tracking soft start-up is

providedfortrackingandsequencingapplications.Safetyfea-

turesincludeoutputovervoltageprotection, programmable

current limit with foldback, and power good monitoring.

L, LT, LTC, LTM, OPTI-LOOP, Linear Technology and the Linear logo are registered trademarks

Q

APPLICATIONS

n

Distributed Power System

and Hot Swap and No R

is a trademark of Linear Technology Corporation. All other

SENSE

n

trademarks are the property of their respective owners. Protected by U.S. Patents including

54811ꢀ8, 548ꢀ554, 6580258, 6304066, 64ꢀ6589, 6ꢀꢀ4611.

Point-of-Load Converters

n

Servers

TYPICAL APPLICATION

Efficiency and Power Loss

vs Load Current

High Efficiency High Power Step-Down Converter

INTV

CC

PV

SV

100

90

80

ꢀ0

60

50

40

30

20

10

0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

IN

V

IN

4.5V TO 24V

PULSE-SKIPPING MODE

+

0.1μF

82μF

LTC3613

PGOOD

100k

V

OUT

–

10Ω

0.4ꢀμH

SENSE

RUN

1000pF

0.1μF

FORCED

CONTINUOUS

MODE

+

V

RNG

V

1.5V

15A

1.5mΩ

OUT

MODE/PLLIN

SW

0.1μF

EXTV

CC

15k

TRACK/SS

BOOST

4ꢀpF

V

= 12V

OUT

IN

10k

V

= 1.5V

INTV

CC

+

2ꢀ0pF

4.ꢀμF

330μF

×2

0.01

0.1

1

10

21k

PGND

ITH

LOAD CURRENT (A)

115k

3613 TA01a

+

OSNS

–

RT

SGND

V

OSNS

3613 TA01

3613fa

1

LTC3613

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

Supply Voltage (PV , SV )....................... –0.3V to 24V

IN

Boost Voltage ............................................ –0.3V to 30V

SW Voltage ................................................ –0.3V to 24V

INTV , EXTV , (BOOST-SW), MODE /PLLIN,

PV

1

2

3

4

5

6

7

8

9

44 PGND

43 PGND

42 PGND

41 PGND

40 PGND

39 PGND

38 PGND

37 PGND

36 PGND

35 SW

IN

CC

V

, PGOOD, RUN Voltages....................... –0.3V to 6V

RNG

+

–

, V

Voltages ........ –0.6V to (INTV + 0.3V)

PV

57

SW

58

OSNS

CC

IN

+,

–

, SENSE SENSE Voltages ................. –0.6V to 6V

OUT

RT, ITH Voltages .....................–0.3V to (INTV + 0.3V)

CC

TRACK/SS Voltages..................................... –0.3V to 5V

Operating Junction Temperature Range

SW 10

BOOST 11

SGND 12

34 INTV

33 INTV

CC

(Notes 2, 4)............................................ –40°C to 125°C

Storage Temperature Range .................. –65°C to 150°C

PGOOD 13

32 SV

IN

SGND

59

+

SNS 14

31 MODE/PLLIN

30 EXTV

–

SNS 15

CC

SGND 16

29 SGND

WKH PACKAGE

56-LEAD (7mm × 9mm) MULTIPAD QFN

T

= 125°C, θ = 29°C/W

JA

JMAX

ORDER INFORMATION

LEAD FREE FINISH

LTC3613EWKH#PBF

LTC3613IWKH#PBF

TAPE AND REEL

PART MARKING*

LTC3613WKH

PACKAGE DESCRIPTION

TEMPERATURE RANGE

–40°C to 125°C

LTC3613EWKH#TRPBF

LTC3613IWKH#TRPBF

56-Lead (ꢀmm × 9mm) Plastic QFN

–40°C to 125°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

3613fa

2

LTC3613

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. SV_IN= 15V, V_FB= V_OSNS⁺– V_OSNS^–, unless otherwise noted. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Main Control Loop

l

V

Input Voltage Operating Range

Output Voltage Operating Range

4.5

0.6

24

V

IN

5.5

OUT

I

Input DC Supply Current

Normal

Q

MODE/PLLIN = INTV

RUN = 0V

2

15

4

25

mA

μA

CC

Shutdown Supply Current

V

REG

Regulated Differential Feedback Voltage

I

= 1.2V (Note 3)

TH

+

–

(V

– V

)

T = 25°C

0.5985

0.596

0.594

0.6

0.6015

0.604

0.606

V

OSNS

A

l

T = 0°C to 85°C

A

T = –40°C to 125°C

A

Regulated Differential Feedback

V

= 4.5V to 24V, ITH = 0.5V to 1.9V,

IN

–

Voltage Over Line, Load and Common Mode

= 500mV (Note 3)

OSNS

+

–

l

(V

OSNS

– V

)

T = 0°C to 85°C

0.594

0.591

0.6

0.606

0.609

V

OSNS

A

T = –40°C to 125°C

A

t

Minimum On-Time

65

105

1.ꢀ

ns

ON(MIN)

Minimum Off-Time

OFF(MIN)

l

g

Error Amplifier Transconductance

Valley Current Sense Threshold,

I

= 1.2V (Note 3)

1.4

2

mS

m(EA)

TH

l

V

= 2V, V = 0.5ꢀV

80

22

39

100

30

50

120

38

61

mV

SENSE(MAX)

RNG

FB

+

–

V

– V

,

= 0V, V = 0.5ꢀV

SENSE

FB

Peak Current = Valley + Ripple

= INTV , V = 0.5ꢀV

CC FB

+

Minimum Current Sense Threshold,V

–

V

= 2V, V = 0.63V

–50

–15

–25

mV

SENSE(MIN)

SENSE

RNG

FB

–

V

SENSE

, Force Continuous Operation

= 0V, V = 0.63V

FB

= INTV , V = 0.63V

CC FB

+

–

l

SENSE , SENSE Voltage Range (Common

Mode)

–0.5

5.5

V

SENSE(CM)

SENSE

+

–

I

SENSE , SENSE Input Bias Current

V

= 0.6V

= 5V

5

1

50

4

nA

μA

SENSE(CM)

V

RUN Pin On Threshold

RUN Pin Hysteresis

V

Rising

RUN

1.1

3.4

1.2

80

1.3

V

mV

μA

RUN(TH)

RUN(HYS)

I

Soft-Start Charging Current

V

= 0V

TRACKSS

1.0

SS

l

UVLO

INTV Undervoltage Lockout

Falling

Rising

3.65

4.2

4.0

4.5

V

CC

INTV Undervoltage Lockout Release

CC

+

–

+

I

V

Input Bias Current

V

= 0.6V

5

25

nA

μA

VOSNS

OSNS

FB

–

V

= 0.6V

–15

–50

3613fa

3

LTC3613

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the specified operating

junction temperature range, otherwise specifications are at T_A= 25°C. SV_IN= 15V, V_FB= V_OSNS⁺– V_OSNS^–, unless otherwise noted. (Note 4)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

Oscillator and Clock Synchronization

f

Free Running Switching Frequency

R = 205k

1ꢀ5

450

900

200

500

1000

225

550

1100

kHz

OSC

T

R = 80.6k

T

R = 38.8k

T

CLK

Clock Input High Level Into Mode/PLLIN

Clock Input Low Level Into Mode/PLLIN

2

V

IH

0.5

IL

Internal V Regulator and External V

CC

INTV

Internal V Voltage

6V < V < 24V

5.1

4.4

5.3

–1

5.55

–2

V

7

CC

IN

Internal V Load Regulation

I

CC

= 0mA to 50mA

CC(7)

CC

EXTV

EXTV Switchover Voltage

EXTV Rising

4.6

200

4.ꢀ5

V

CC(TH)

CC

EXTV Switchover Hysteresis

mV

CC(HYS)

CC

ΔINTV

EXTV Voltage Drop

V = 5V. I = 50mA

EXTVCC CC

CC

PGOOD Output

PGD

PGOOD Upper Threshold

PGOOD Lower Threshold

V

Rising (With Respect to Regulated

FB

5

ꢀ.5

10

–5

7

OV

Feedback Voltage V

)

REG

V

FB

Falling (With Respect to Regulated

–10

–ꢀ.5

UV

Feedback Voltage V

)

REG

PGOOD Hysteresis

V

FB

Returning

2

0.15

20

7

V

HYS

V

PGOOD Low Voltage

I

= 5mA

0.4

PGD(LO)

PGOOD

t

Delay from OV/UV Fault to PGOOD Falling

(Note 5)

μs

PGD(FALL)

PGD(RISE)

Delay from OV/UV Recovery to PGOOD Rising (Note 5)

10

R

DS(ON)

R

Top Switch On-Resistance

Bottom Switch On-Resistance

ꢀ.5

5.5

mohm

DS(ON)

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: The LTC3613 is tested under pulsed load conditions such that

T ≈ T . The LTC3613E is guaranteed to meet specifications from

J

A

0°C to 125°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LTC3613I is guaranteed over the full –40°C to 125°C operating junction

temperature range. Note that the maximum ambient temperature

consistent with these specifications is determined by specific operating

conditions in conjunction with board layout, the rated package thermal

impedance and other environmental factors.

Note 2: T is calculated from the ambient temperature, T , and power

J

A

dissipation, P , as follows:

D

T = T + (P • 29°C/W) (θ is simulated per JESD51-ꢀ high effective

J

A

D

JA

thermal conductivity test board)

θ

=1°C/W (θ is simulated when heat sink is applied at the bottom

JC

of the package.)

Note 5: Delay times are measured using 507 levels.

+

Note 3: The LTC3613 is tested in a feedback loop that adjusts V = V

FB

OSNS

–

– V

to achieve a specified error amplifier output voltage (ITH).

OSNS

3613fa

4

LTC3613

TYPICAL PERFORMANCE CHARACTERISTICS T_A= 25°C unless otherwise noted

Transient Response:

Forced Continuous Mode

Load Step:

Forced Continuous Mode

Load Release:

Forced Continuous Mode

V

OUT

V

OUT

V

100mV/DIV

OUT

100mV/DIV

I

L

I

L

10A/DIV

I

LOAD

I

LOAD

10A/DIV

3613 G01

3613 G02

3613 G03

40μs/DIV

10μs/DIV

LOAD TRANSIENT = 0A TO 15A

LOAD STEP = 0A TO 15A

LOAD RELEASE = 15A TO 0A

V

= 12V, V

= 1.5V

V

= 12V, V

= 1.5V

V

= 12V, V

= 1.5V

IN

OUT

IN

OUT

IN

OUT

FIGURE 10 CIRCUIT

Transient Response:

Pulse-Skipping Mode

Load Release:

Pulse-Skipping Mode

Load Step: Pulse-Skipping Mode

V

OUT

V

OUT

100mV/DIV

I

L

I

L

10A/DIV

I

LOAD

I

LOAD

10A/DIV

3613 G04

3613 G05

3613 G06

40μs/DIV

10μs/DIV

LOAD TRANSIENT = 500mA TO 15A

LOAD STEP = 500mA TO 15A

LOAD RELEASE = 15A TO 500mA

V

= 12V, V

= 1.5V

V

= 12V, V

= 1.5V

V

= 12V, V

= 1.5V

IN

OUT

IN

OUT

IN

OUT

FIGURE 10 CIRCUIT

Soft Start-Up into

a Pre-Biased Output

Normal Soft Start-Up

Output Tracking

V

IN

V

IN

5V/DIV

TRACK/SS

500mV/DIV

TRACK/SS

500mV/DIV

TRACK/SS

500mV/DIV

V

OUT

V

OUT

1V/DIV

V

OUT

V

PRE-BIASED TO 0.ꢀ5V

OUT

1V/DIV

3613 G0ꢀ

3613 G08

3613 G09

4ms/DIV

V

= 12V

OUT

FIGURE 10 CIRCUIT

2ms/DIV

V

= 12V

10ms/DIV

V

= 12V

IN

OUT

IN

OUT

= 1.5V

FIGURE 10 CIRCUIT

3613fa

5

LTC3613

TYPICAL PERFORMANCE CHARACTERISTICS T_A= 25°C unless otherwise noted

Overcurrent Protection

Short-Circuit Protection

Overvoltage Protection

SHORT-

CIRCUIT

TRIGGER

V

OUT

LOAD-STEP

TRIGGER

V

DROOPS

OUT

SHORT-CIRCUIT

REGION

ꢀ.5A

200mV/DIV

DUE TO

REACHING CURRENT LIMIT

V

OVERVOLTAGE

TRIGGER

OUT

OVERVOLTAGE REGION

V

OUT

1V/DIV

I

L

NOTE

10A/DIV

I

LOAD

10A/DIV

SW

20V/DIV

I

LOAD

10A/DIV

3613 G10

3613 G11

3613 G12

V

= 12V

OUT

FIGURE 10 CIRCUIT

4ms/DIV

V

= 12V

200μs/DIV

V

= 12V

20μs/DIV

IN

OUT

IN

OUT

= 1.5V

FIGURE 10 CIRCUIT

NOTE: SW IS FORCED LOW

FOR EXTENDED PERIODS TO

REMOVE OVERVOLTAGE

NOTE: INDUCTOR CURRENT REACHES

CURRENT LIMIT BEFORE FOLDBACK

AND DURING SHORT-CIRCUIT RECOVERY

Output Regulation

vs Input Voltage

Output Regulation

vs Load Current

Output Regulation

vs Temperature

0.2

0.1

0

0.5

0.3

0.5

0.3

V

I

= 12V

= 5A

V

I

= 12V

= 0A

IN

LOAD

V

I

= 12V

= 4A

IN

LOAD

FIGURE 10 CIRCUIT

V

NORMALIZED AT T = 25°C

FIGURE 10 CIRCUIT

OUT

A

FIGURE 10 CIRCUIT

0.1

–0.1

–0.3

–0.5

–0.1

–0.3

–0.5

–0.1

–0.2

–50 –25

0

25 50 55 100 125 150

TEMPERATURE (°C)

0

4

8

12

16

20

24

0

3

6

9

12

15

INPUT VOLTAGE (V)

LOAD CURRENT (A)

3613 G15

3613 G13

3613 G14

Switching Frequency

vs Input Voltage

Switching Frequency

vs Load Current

Non-Synchronized Switching

Frequency vs Temperature

0.5

0.3

2.0

1.5

1.0

0.5

0

1.0

0.5

V

I

= 12V

= 0A

V

I

= 12V

= 4A

IN

LOAD

IN

LOAD

FREQUENCY NORMALIZED AT T = 25°C

A

FIGURE 10 CIRCUIT

0

0.1

–0.5

–1.0

–1.5

–2.0

–0.1

–0.3

–0.5

V

LOAD

FIGURE 10 CIRCUIT

= 12V

IN

–0.5

–1.0

I

= 5A

12

(V)

16

0

3

6

9

12

15

0

4

8

20

24

ꢀ5 100

125 150

–50 –25

0

25 50

V

TEMPERATURE (°C)

LOAD CURRENT (A)

IN

3613 G1ꢀ

3613 G16

3613 G18

3613fa

6

LTC3613

TYPICAL PERFORMANCE CHARACTERISTICS T_A= 25°C unless otherwise noted

Error Amplifier Transconductance

vs Temperature

Current Sense Voltage

vs ITH Voltage

Maximum Current Sense Voltage

vs Temperature

120

100

80

1.80

1.ꢀ5

1.ꢀ0

1.65

1.60

1.55

1.50

120

100

80

60

40

20

0

V

= 2V

RNG

60

40

V

= 1V

20

RNG

0

V

= 0.6V

= 0.9V

= 1.3V

= 1.6V

= 2.0V

V

= 0.6V

RNG

–20

–40

–60

ꢀ5 100

–50 –25

0

25 50

125 150

ꢀ5 100

125 150

–50 –25

0

25 50

0

2

2.5

0.5

1

1.5

TEMPERATURE (°C)

ITH VOLTAGE (V)

3613 G22

3613 G24

3613 G23

Input Undervoltage Lockout

Thresholds vs Temperature

RUN and TRACK/SS Pull-Up

Currents vs Temperature

RUN Thresholds vs Temperature

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

4.5

4.3

4.1

3.9

3.ꢀ

3.5

3.3

1.8

1.6

1.4

1.2

1.0

0.8

0.6

SWITCHING REGION

UVLO RELEASE

(INTV RISING)

CC

RUN

STANDBY REGION

UVLO LOCK

TRACK/SS

(INTV FALLING)

CC

SHUTDOWN REGION

50 ꢀ5

TEMPERATURE (°C)

ꢀ5 100

125 150

–50 –25

0

25

100 125 150

–50 –25

0

25 50

125 150

–50 –25

0

25 50

TEMPERATURE (°C)

3613 G25

3613 G26

3613 G2ꢀ

3613fa

7

LTC3613

PIN FUNCTIONS

PV (Pins 1-9, 53-56, 57 Exposed Pad): Power Supply

V

(Pin 18): Output voltage sense for adjusting the

IN

OUT

Inputs. These pins connect to the drain of the internal

on-timeforconstantfrequencyoperation. Tyingthispinto

the local output (instead of the remote output) is recom-

mendedformostapplications.Thispincanbeprogrammed

as needed for achieving the steady-state on-time required

for constant frequency operation.

powerMOSFETS. ThePV exposedpadmustbesoldered

IN

to the circuit board for electrical contact and rated thermal

performance. The supply voltage can range from 4.5V to

24V. The voltage on this pin is also used to adjust the TG

on-timeinordertomaintainconstantfrequencyoperation.

–

V

(Pin 20): Differential Output Sensing (–) Input.

OSNS

SW (Pins 10, 35, 45-51, 58 Exposed Pad): Switch Node

Connect this pin to the negative terminal of the output

capacitor. There is a bias current of 35μA (typical) flowing

out of this pin.

Connection. The (–) terminal of the bootstrap capacitor,

C , connects to this node. This pin swings from a diode

B

voltagebelowgrounduptoV .TheSWexposedpadmust

+

IN

V

(Pin 21): Differential Output Sensing (+) Input.

OSNS

be soldered to the circuit board for electrical contact and

Connect this pin to the feedback resistor divider between

the positive and negative output capacitor terminals. In

normal operation the LTC3613 will regulate the differen-

tial output voltage which is divided down to 0.6V by the

feedback resistor divider.

rated thermal performance.

BOOST (Pin 11): Boosted Driver Supply Connection. The

(+) terminal of the bootstrap capacitor, C , as well as

B

the cathode of the Schottky diode, D , connects to this

B

node. This node swings from INTV – V

to V

CC

SCHOTTKY

IN

TRACK/SS(Pin22):ExternalTrackingandSoft-StartInput.

The LTC3613 regulates the differential feedback voltage

+ INTV – V

.

CC

SCHOTTKY

+

–

SGND (Pins 12, 16, 17, 19, 28, 29, 59 Exposed Pad):

Signal Ground Connection. The SGND exposed pad must

be soldered to the circuit board for electrical contact and

rated thermal performance. All small-signal components

should be connected to the signal ground. Connect signal

ground to power ground only at one point using a single

PCB trace.

(V

− V

) to the smaller of 0.6V or the voltage

OSNS

on the TRACK/SS pin. An internal 1.0ꢁA pull-up current

source is connected to this pin. A capacitor to ground at

this pin sets the ramp time to the final regulated output

voltage. Alternatively, another voltage supply connected

through a resistor divider to this pin allows the output to

track the other supply during start-up.

PGOOD (Pin 13): Power Good Indicator Output. This

open-drain logic output is pulled to ground when the

output voltage is outside of a ꢀ.57 window around the

regulation point.

ITH(Pin23):CurrentControlVoltageandSwitchingRegu-

lator Compensation Point. The current sense threshold

increases with this control voltage which ranges from

0V to 2.4V.

+

SENSE (Pin 14): Differential Current Sensing (+) Input.

V

(Pin 24): Current Sense Voltage Range Input. The

RNG

+

For R

current sensing, Kelvin (4-wire) connect

maximum allowed sense voltage between SENSE and

SENSE

+

–

SENSE and SENSE pins across the sense resistor. For

SENSE is equal to 0.05 • V

. If V

is tied to SGND,

RNG

+

–

DCR sensing, Kelvin connect SENSE and SENSE pins

across the sense filter capacitor.

the device operates with a maximum sense voltage of

30mV. If V

a maximum sense voltage of 50mV.

is tied to INTV , the device operates with

RNG

CC

–

SENSE (Pin 15): Differential Current Sensing (–) Input.

For R

current sensing, Kelvin (4-wire) connect the

RT (Pin 25): Switching Frequency Programming Pin.

Connect an external resistor from RT to signal ground to

program the switching frequency between 200kHz and

1MHz. An external clock applied to MODE/PLLIN must

be within 307 of this free-running frequency to ensure

frequency lock.

SENSE

+

–

SENSE and SENSE pins across the sense resistor. For

+

–

DCRsensing,KelvinconnecttheSENSE andSENSE pins

across the sense filter capacitor.

3613fa

8

LTC3613

PIN FUNCTIONS

RUN (Pin 26): Digital Run Control Input. RUN self biases

high with an internal 1.3μA pull-up. Forcing RUN below

1.2V disables switching. Taking RUN below 0.ꢀ5V shuts

down all bias and places the LTC3613 into micropower

shutdown mode of approximately 15ꢁA.

detectedorMODE/PLLINistiedtoINTV ,forcedcontinu-

CC

ous mode operation is selected. Tying this pin to SGND

allows discontinuous pulse-skipping mode operation at

light loads.

SV (Pin 32): Signal Input Supply. This pin powers the

IN

EXTV (Pin30):ExternalV Input.WhenEXTV exceeds

internal control circuitry.

CC

4.6V, an internal switch connects this pin to INTV and

CC

INTV (Pins 33, 34): Internal 5.3V Regulator Output. The

CC

shutsdowntheinternalregulatorsothatthecontrollerand

driver and control circuits are powered from this voltage.

gate drive power is drawn from EXTV . EXTV should

CC

Decouple this pin to power ground with a minimum of

not exceed V .

IN

4.ꢀꢁFceramiccapacitor(C ).TheanodeoftheSchottky

VCC

MODE/PLLIN (Pin 31): External Clock Synchronization

Input and/or Forced Continuous Mode Input. When an

external clock is applied to this pin, the rising switching

cycle will be synchronized with the rising edge of the

external clock. Additionally, this pin determines operation

under light load conditions. When either a clock input is

diode, D , connects to this pin.

B

PGND (Pins 36-44): Power Ground Connection. Connect

this pin as close as practical to the (–) terminal of C

VCC

and the (–) terminal of C .

IN

3613fa

9

LTC3613

FUNCTIONAL DIAGRAM

V

IN

C

IN

PV

IN

SV

IN

INPUT SUPPLY

IN

LDO

OUT EN

C

IN

BO0ST

UVLO

D

B

+

–

3.65V

4.2V

TG DRV

MT

C

B

L

R

SENSE

SW

V

OUT

EXTV

CC

1.3μA

+

–

RUN

+

4.6V

0.ꢀ5V

1.2V

–

C

OUT

START

STOP

–

LOGIC

CONTROL

INTV

CC

INTV

MB

CC

V

OUT

ONE-SHOT

TIMER

R

FB2

FB1

C

VCC

BG DRV

TIME

ADJUST

PGND

I

REV

CMP

–

+

–

+

CLOCK

MODE/PLLIN

RT

CLOCK

DETECT

PLL

SYSTEM

+

SENSE

–

SENSE

OSCILLATOR

1μA

RT

TRACK/SS

+

–

C

SS

0.6V

INTV

CC

V

OSNS

+

–

0.645V

+

OV

–

R

PGD

DA

(A = 1)

PGOOD

EA

m(EA)

–

(g

= 1.ꢀmS)

V

OSNS

3613 FD

+

UV

–

0.555V

V

ITH SGND

RNG

INTV

CC

R1

R

ITH

C

ITH1

R2

(Refer to Functional Diagram)

OPERATION

Main Control Loop

Innormalsteady-stateoperation,thetopMOSFETisturned

on for a fixed time interval proportional to the delay in the

one-shot timer. The PLL system adjusts the delay in the

one-shot timer until the top MOSFET turn-on is synchro-

nized either to the internal oscillator or the external clock

input if provided. As the top MOSFET turns off, the bottom

MOSFET turns on with a small time delay (dead time) to

avoid shoot-through current. The next switching cycle is

The LTC3613 uses valley current mode control to regulate

the output voltage in a monolithic, all N-channel MOSFET

DC/DCstep-downconverter.Currentcontrolisachievedby

sensing the inductor current across SENSE and SENSE ,

eitherbyusinganexplicitresistorconnectedinserieswith

the inductor or by implicitly sensing the inductor’s resis-

tive (DCR) voltage drop through an RC filter connected

across the inductor.

+

–

initiated when the current comparator, I

, senses that

CMP

inductor current has reached the valley threshold point

3613fa

10

LTC3613

(Refer to Functional Diagram)

OPERATION

and turns the bottom MOSFET off immediately and the

top MOSFET on. Again in order to avoid shoot-through

current there is a small dead time delay before the top

MOSFET turns on.

The top MOSFET driver is biased from the floating boot-

strap capacitor, C , which normally recharges during

B

each off cycle through an external Schottky diode when

the top MOSFET turns off. If the V voltage is low and

IN

INTV drops below 3.65V, undervoltage lockout circuitry

CC

The voltage on the ITH pin sets the I

valley threshold

CMP

disables the external MOSFET driver and prevents the

point. The error amplifier, EA, adjusts this ITH voltage

power switches from turning on.

+

by comparing the differential feedback signal, V

−

OSNS

–

V

OSNS

,toa0.6Vinternalreferencevoltage.Consequently,

Shutdown and Start-Up

the LTC3613 regulates the output voltage by forcing the

differentialfeedbackvoltagetobeequaltothe0.6Vinternal

reference. The difference amplifier, DA, converts the dif-

ferential feedback signal to a single-ended input for the

EA. If the load current increases, it causes a drop in the

differential feedback voltage relative to the reference. The

EA forces ITH voltage to rise until the average inductor

current again matches the load current.

The LTC3613 can be shut down using the RUN pin. Pull-

ing this pin below 1.2V prevents switching, and less than

0.ꢀ5Vdisablesmostoftheinternalbiascircuitry,including

the INTV regulator. When RUN is less than 0.ꢀ5V, the

CC

shutdown I is about 15ꢁA. Pulling the RUN pin between

Q

0.ꢀ5Vand1.2Venablesthecontrollerintoastandbymode

where all internal circuitry is powered-up except for the

MOSFET driver. The standby I is about 2mA. Releasing

Q

Differential Output Sensing

the RUN pin from ground allows an internal 1.3ꢁA current

to pull the pin above 1.2V and fully enable the controller

including the MOSFET driver. Alternatively, the RUN pin

may be externally pulled up or driven directly by logic. Be

careful not to exceed the absolute maximum rating of 6V

on this pin. When pulled up by a resistor to an external

voltage, theRUNpinwillsinkabout35μAofcurrentbefore

Theoutputvoltageisresistivelydividedexternallytocreate

afeedbackvoltageforthecontroller.Theinternaldifference

amplifier, DA, senses this feedback voltage along with the

output’s remote ground reference to create a differential

feedback voltage. This scheme overcomes any ground

offsets between local ground and remote output ground,

resulting in a more accurate output voltage. The LTC3613

allows for remote output ground deviations as much as

500mV with respect to local ground.

reaching 6V. If the external voltage is above 6V (e.g., V ),

IN

select a large enough resistor value so that the voltage on

RUN will not exceed 6V.

The start-up of the output voltage, V , is controlled by

OUT

INTV /EXTV Power

the voltage on the TRACK/SS pin. When the voltage on

the TRACK/SS pin is less than the 0.6V internal reference,

the LTC3613 regulates the differential feedback voltage to

the TRACK/SS voltage instead of the 0.6V reference. This

allows the TRACK/SS pin to be used for programming a

CC

Power for the top and bottom MOSFET drivers and most

otherinternalcircuitryisderivedfromtheINTV pin.Power

CC

on the INTV pin is derived in two ways: if the EXTV

CC

pin is below 4.6V, then an internal 5.3V low dropout linear

ramp-uptimeforV

byconnectinganexternalcapacitor

OUT

regulator, LDO, supplies INTV power from PV ; if the

CC

IN

from the TRACK/SS pin to SGND. An internal 1ꢁA pull-up

current charges this capacitor, creating a voltage ramp on

the TRACK/SS pin. As the TRACK/SS voltage rises from

0V to 0.6V (and beyond), the LTC3613 forces the output

EXTV pin is tied to an external source larger than 4.6V,

CC

then the LDO is shut down and an internal switch shorts

the EXTV pin to the INTV pin, thereby powering the

CC

INTV pinwiththeexternalsourceandhelpingtoincrease

CC

voltage, V , to ramp up smoothly to its final value.

OUT

overallefficiencyanddecreaseinternalselfheatingthrough

power dissipated in the LDO. This external power source

could be the output of the step-down switching regulator

itself if the output is programmed to higher than 4.6V.

Alternatively, the TRACK/SS pin can be used to track the

start-up of V

to another external supply as in a master

OUT

slave configuration. Typically, this requires connecting a

resistor divider from the master supply to the TRACK/SS

pin (see Soft-Start and Tracking).

3613fa

11

LTC3613

OPERATION

When the RUN pin is pulled low to disable the controller or

switching cycle turn-on to the rising edge of the clock.

The LTC3613 operates in forced continuous mode when

itissynchronizedtotheexternalclock. Theexternalclock

frequency has to be within 307 of the internal oscillator

frequency for successful synchronization and the clock

input levels should be greater than 2V for HI and less

than 0.5V for LO. The MODE/PLLIN pin has an internal

600kΩ pull-down resistor.

whenINTV dropsbelowitsundervoltagelockoutthresh-

CC

old of 3.65V, the TRACK/SS pin is pulled low internally.

Light Load Current Operation

When the DC load current is less than 1/2 of the peak-

to-peak inductor current ripple, the inductor current can

drop to zero or become negative. If the MODE/PLLIN pin

is connected to SGND, the LTC3613 will transition into

discontinuousmodeoperation(alsocalledpulse-skipping

mode),whereacurrentreversalcomparator,I_REV,detects

and prevents negative inductor current by shutting off the

bottom MOSFET, MB. In this mode, both switches remain

off with the output capacitor supplying the load current.

As the output capacitor discharges and the output volt-

age droops lower, the EA will eventually move the ITH

voltage above the zero current level to initiate another

switching cycle.

Power Good and Fault Protection

The power good pin, PGOOD, is connected internally to an

open-drainN-channelMOSFET.Anexternalpull-upresistor

to a voltage supply of up to 6V (or INTV ) completes the

CC

powergooddetectionscheme.Overvoltageandundervolt-

age comparators OV and UV turn on the MOSFET and pull

the PGOOD pin low when the differential feedback voltage

is outside a ꢀ.57 window of the 0.6V reference voltage.

The PGOOD pin is also pulled low when the LTC3613 is

in the soft-start or tracking phase, when in undervoltage

lockout, or when the RUN pin is low (shut down).

If the MODE/PLLIN pin is tied to INTV or an external

CC

clockisappliedtoMODE/PLLIN,theLTC3613willbeforced

to operate in continuous mode (forced continuous mode)

and not transition into discontinuous mode. In this case

When the differential feedback voltage is within the ꢀ.57

requirement, the open-drain NMOS is turned off and the

pin is pulled up by an external resistor. There is an internal

delay of 10μs before the PGOOD pin will indicate power

good once the differential feedback voltage is within the

ꢀ.57 window. When the feedback voltage goes out of

the ꢀ.57 window, there is an internal 20ꢁs delay before

PGOOD is pulled low. In an overvoltage condition, MT is

turned off and MB is turned on immediately without any

delay and held on until the overvoltage condition clears.

thecurrentreversalcomparator,I ,isdisabled,allowing

REV

theinductorcurrenttobecomenegativeandthusmaintain

constant frequency operation.

Frequency Selection and External Clock

Synchronization

The steady-state switching frequency of the LTC3613 is

set by an internal oscillator. The frequency of this internal

oscillator can be programmed from 200kHz to 1MHz by

connecting a resistor from the RT pin to SGND. The RT

pin is forced to 1.2V internally. A phase-locked loop (PLL)

system synchronizes the turn-on of the switching cycle to

this internal oscillator when no external clock is provided.

Foldbackcurrentlimitingisprovidediftheoutputisshorted

to ground. As the differential feedback voltage drops, the

current threshold voltage on the ITH pin is pulled down

and clamped to 1.2V. This reduces the inductor valley

current level to one-fourth of its maximum value as the

differential feedback approaches 0V. Foldback current

limiting is disabled at start-up.

For applications with stringent frequency or interfer-

ence requirements, an external clock source connected

to the MODE/PLLIN pin can be used to synchronize the

3613fa

12

LTC3613

APPLICATIONS INFORMATION

The Typical Application on the first page of this data sheet

is a basic LTC3613 application circuit. The LTC3613 can

be configured to sense the inductor current either through

SW

LTC3613

V

OUT

C

FF

R

a series sense resistor, R

, or through an RC filter

FB2

(OPT)

SENSE

+

–

C

V

OUT

OSNS

across the inductor (DCR). The choice between the two

current sensing schemes is largely a design trade-off

between cost, power consumption and accuracy. DCR

sensing is becoming popular because it saves expensive

current sensing resistors and is more power efficient,

especially in high current applications. However, cur-

rent sensing resistors provide the most accurate current

limits for the controller. Once the required output voltage

and operating frequency have been determined, external

component selection is driven by load requirements, and

begins with the selection of inductor and current sensing

components. Next, the proper current sense threshold is

FB1

3613 F01

V

Figure 1. Setting Output Voltage

+

The V

pin is high impedance with no input bias cur-

OSNS

–

rent. The V

pin has about 35ꢁA of current flowing

OSNS

out of the pin.

Differentialoutputsensingallowsformoreaccurateoutput

regulation in high power distributed systems having large

line losses. Figure 2 illustrates the potential variations in

the power and ground lines due to parasitic elements.

These variations are exacerbated in multi-application

systems with shared ground planes. Without differential

outputsensing, thesevariationsdirectlyreflectasanerror

in the regulated output voltage. The LTC3613’s differential

output sensing can correct for up to 500mV of variation

in the output’s power and ground lines.

programmed using the V

capacitors are selected.

pin. Finally, input and output

RNG

Output Voltage Programming and

Differential Output Sensing

The LTC3613 integrates differential output sensing with

output voltage programming, allowing for simple and

seamless design. As shown in Figure 1, the output voltage

is programmed by an external resistor divider from the

The LTC3613’s differential output sensing scheme is

distinct from conventional schemes where the regulated

output and its ground reference are directly sensed with

a difference amplifier whose output is then divided down

with an external resistive divider and fed into the error

amplifier input. This conventional scheme is limited by

the common mode input range of the difference amplifier

and typically limits differential sensing to the lower range

of output voltages.

regulated output point to its ground reference. The resis-

+

tive divider is tapped by the V

pin, and the ground

OSNS

–

reference is sensed by V

. An optional feed-forward

capacitor, C , can be used to improve the transient per-

OSNS

FF

formance of the regulator system as discussed under

OPTI-LOOP^®Compensation. The resulting output voltage

is given according to the following equation:

⎛

⎞

⎟

⎠

R_FB2

R_FB1

The LTC3613 allows for seamless differential output

sensing by sensing the resistively divided feedback volt-

age differentially. This allows for differential sensing in

the full output range from 0.6V to 5.5V. The difference

amplifier of the LTC3613 has a –3dB bandwidth of 8MHz,

high enough to not affect main loop compensation and

transient behavior.

V_OUT=0.6V• 1+

⎜

⎝

Moreprecisely,theV valueprogrammedintheprevious

OUT

equation is with respect to the output’s ground reference,

and thus is a differential quantity. For example, if V

OUT

is programmed to 5V and the output ground reference

is at –0.5V, then the output will be 4.5V with respect to

signal ground. The minimum differential output voltage is

limited to the internal reference, 0.6V, and the maximum

differential output voltage is 5.5V.

3613fa

13

LTC3613

APPLICATIONS INFORMATION

+

C

IN

V

C

IN

PV

IN

–

POWER TRACE

PARASITICS

L

LTC3613

+

SW

V

DROP(PWR)

–

V

OSNS

I

OSNS

PGND

LOAD

C

OUT1

OUT2

I

LOAD

R

FB1

FB2

GROUND TRACE

PARASITICS

V

DROP(GND)

OTHER CURRENTS

FLOWING IN

SHARED GROUND

PLANE

3613 F02

Figure 2. Differential Output Sensing Used to Correct Line Loss Variations

in a High Power Distributed System with a Shared Ground Plane

+

To avoid noise coupling into V

, the resistor divider

Not counting resistor tolerances, the switching fre-

quency could still have a 107 deviation from the ideal

programmed value. The internal PLL has a synchroniza-

tion range of 307 around this programmed frequency.

Therefore, during external clock synchronization be sure

thattheexternalclockfrequencyiswithinthis 307range

of the RT programmed frequency. It is advisable that the

RT programmed frequency be equal to the external clock

for maximum synchronization margin. Refer to Phase and

Frequency Synchronization for further details.

OSNS

+

–

should be placed near the V

and V

pins and

OSNS

physically close to the LTC3613. The remote output and

ground traces should be routed together as a differential

pair to the remote output. These traces should be termi-

nated as close as physically possible to the remote output

point that is to be accurately regulated through remote

differential sensing.

Switching Frequency Programming

The choice of operating frequency is a trade-off between

efficiencyandcomponentsize.Loweringtheoperatingfre-

quencyimprovesefficiencybyreducingMOSFETswitching

losses but requires larger inductance and/or capacitance

to maintain low output ripple voltage. Conversely, raising

the operating frequency degrades efficiency but reduces

component size.

Inductor Selection

The operating frequency and inductor selection are inter-

relatedinthathigheroperatingfrequenciesallowtheuseof

smaller inductor and capacitor values. A higher frequency

generally results in lower efficiency because of MOSFET

gate charge losses and top MOSFET transition losses.

In addition to this basic trade-off, the effect of inductor

value on ripple current and low current operation must

also be considered.

The switching frequency of the LTC3613 can be pro-

grammed from 200kHz to 1MHz by connecting a resistor

from the RT pin to signal ground. The value of this resistor

is given by the following empirical formula:

41550

R kꢂ =

–2.2

[

]

T

f kHz

[

]

3613fa

14

LTC3613

APPLICATIONS INFORMATION

The inductor value has a direct effect on ripple current.

rent comparators is –0.5V to 5.5V. Both SENSE pins are

high impedance inputs. When the common mode range

is between –0.5V to 1.1V, there is no input bias current,

and when between 1.4V and 5.5V, there is less than 1ꢁA

of current flowing into the pins. Between 1.1V and 1.4V,

the input bias current will be zero if the common mode

voltage is ramped up from 1.1V and less than 1ꢁA if the

common mode voltage is ramped down from 1.4V. The

high impedance inputs to the current comparator allow

accurate DCR sensing. However, care must be taken not

to float these pins during normal operation.

The inductor ripple current, ΔI , decreases with higher

L

inductance or frequency and increases with higher V :

IN

⎛

⎞

⎟

⎠

V_OUT

f•L

V_OUT

ΔI_L=

• 1–

⎜

⎝

V

IN

Accepting larger values of ΔI allows the use of low induc-

L

tances, but results in higher output voltage ripple, higher

ESRlossesintheoutputcapacitor,andgreatercorelosses.

A reasonable starting point for setting ripple current is

ΔI = 0.4 • I

where I

is the maximum

L

OUT(MAX)

ThemaximumallowedsensevoltageV

between

SENSE(MAX)

output current for the application. The maximum ΔI

L

+

–

SENSE and SENSE is set by the voltage applied to the

pin and is given by:

occurs at the maximum input voltage. To guarantee that

ripple current does not exceed a specified maximum, the

inductance should be chosen according to:

V

RNG

V

= 0.05 • V

RNG

SENSE(MAX)

⎛

⎞

The current mode control loop does not allow the induc-

V_OUT

f• ΔI_L(MAX)

V_OUT

V

IN(MAX)

L=

• 1–

⎜

⎟

tor current valleys to exceed 0.05 • V . The maximum

RNG

⎝

⎠

output current is given by:

Once the value for L is known, the type of inductor must

be selected. High efficiency converters generally cannot

tolerate the core loss of low cost powdered iron cores,

forcing the use of more expensive ferrite, molypermalloy

or Kool Mꢁ cores. Ferrite core material saturates hard,

meaning that inductance collapses abruptly when the

peak design current is exceeded. This results in an abrupt

increase in inductor ripple current and consequent output

voltage ripple. Do not allow the core to saturate!

V_SENSE(MAX)

1

I_OUT(MAX)

=

+ ΔI_L

2

R_SENSE

TheV

isshowninthefigure“MaximumCurrent

SENSE(MAX)

SenseVoltagevsTemperature”intheTypicalPerformance

Characteristics. Note that ITH is close to 2.4V when in

current limit.

An external resistive divider from INTV can be used

CC

to set the voltage on the V

pin between 0.6V and 2V,

RNG

A variety of inductors designed for high current, low volt-

ageapplicationsareavailablefrommanufacturerssuchas

Sumida, Panasonic, Coiltronics, Coilcraft, Toko, Vishay,

Pulse and Würth.

resulting in maximum sense voltages between 30mV and

100mV.Thewidevoltagesenserangeallowsforavarietyof

applications. The V

pin can also be tied to either SGND

RNG

or INTV to force internal defaults. When V

is tied to

CC

RNG

SGND, thedeviceoperateswithamaximumsensevoltage

of 30mV. When the V pin is tied to INTV , the device

operates with a maximum sense voltage of 50mV. When

setting current limit, ensure that the junction temperature

does not exceed the rating of 125°C.

Current Sense Pins and Current Limit Programming

RNG

CC

+

Inductor current is sensed through the SENSE and

–

SENSE pins and fed into the internal current compara-

tors. The common mode input voltage range of the cur-

3613fa

15

LTC3613

APPLICATIONS INFORMATION

R

RESISTOR

SENSE

For today’s highest current density solutions the value of

the sense resistor can be less than 1mΩ and the maxi-

mum sense voltage can be as low as 30mV. In addition,

inductor ripple currents greater than 507 with operation

up to 1MHz are becoming more common. Under these

conditions, the voltage drop across the sense resistor’s

parasitic inductance becomes more relevant. A small RC

filter placed near the IC has been traditionally used to re-

duce the effects of capacitive and inductive noise coupled

in the sense traces on the PCB. A typical filter consists of

two series 10Ω resistors connected to a parallel 1000pF

capacitor, resulting in a time constant of 20ns.

AND

PARASITIC INDUCTANCE

R

ESL

V

SW

LTC3613

OUT

R

F

+

SENSE

C

F

–

3613 F03

FILTER COMPONENTS

PLACED NEAR SENSE PINS

Figure 3. R_SENSECurrent Sensing

The filter components need to be placed close to the IC.

The positive and negative sense traces need to be routed

as a differential pair and Kelvin (4-wire) connected to the

sense resistor.

R

Inductor Current Sensing

SENSE

A typical R

showninFigure3. R

inductor current sensing scheme is

SENSE

ischosenbasedontherequired

maximum output current. Given the maximum current,

,maximumsensevoltage,V ,setbythe

I

DCR Inductor Current Sensing

OUT(MAX)

SENSE(MAX)

V

pin, and maximum inductor ripple current, ΔI

,

RNG

L(MAX)

For applications requiring higher efficiency at high load

currents, the LTC3613 is capable of sensing the voltage

drop across the inductor DCR, as shown in Figure 4. The

DCR of the inductor represents the small amount of DC

winding resistance, which can be less than 1mΩ for to-

day’s low value, high current inductors. In a high current

application requiring such an inductor, conduction loss

through a sense resistor would cost several points of

efficiency compared to DCR sensing.

the value of R

can be chosen as:

SENSE

V_SENSE(MAX)

R_SENSE

=

ΔI_L(MAX)

I_OUT(MAX)

–

2

Conversely, given R

and thus the V

above equation. To assure that the maximum rated output

current can be supplied for different operating conditions

andcomponentvariations,sufficientdesignmarginshould

be built into these calculations.

and I

, V

OUT(MAX) SENSE(MAX)

SENSE

voltage could be determined from the

RNG

INDUCTOR

L

DCR

SW

LTC3613

V

OUT

C

OUT

L/DCR = (R1||R2) C1

R1

BecauseofpossiblePCBnoiseinthecurrentsensingloop,

+

the current ripple of ΔV

= ΔI • R

also needs

SENSE

L

SENSE

R2

(OPT)

to be checked in the design to get a good signal-to-noise

C1

–

3613 F04

ratio. In general, for a reasonably good PCB layout, a

10mVΔV

number to start with, either for R

applications.

voltageisrecommendedasaconservative

SENSE

C1 NEAR SENSE PINS

or DCR sensing

SENSE

Figure 4. DCR Current Sensing

3613fa

16

LTC3613

APPLICATIONS INFORMATION

The inductor DCR is sensed by connecting an RC filter

across the inductor. This filter typically consists of one

or two resistors (R1 and R2) and one capacitor (C1) as

showninFigure4.IftheexternalR1||R2•C1timeconstant

is chosen to be exactly equal to the L/DCR time constant,

the voltage drop across the external capacitor is equal

to the voltage drop across the inductor DCR multiplied

by R2/(R1 + R2). Therefore, R2 may be used to scale

the voltage across the sense terminals when the DCR is

greater than the target sense resistance. With the ability

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at the maximum input

voltage:

V

_IN(MAX)–V_OUT• V

(

)

OUT

P

R1 =

_LOSS( )

R1

Ensure that R1 has a power rating higher than this value.

If high efficiency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

R

SENSE

sensing. Light load power loss can be modestly

to program current limit through the V

pin, R2 may

RNG

higher with a DCR network than with a sense resistor due

totheextraswitchinglossesincurredthroughR1.However,

DCR sensing eliminates a sense resistor, reduces conduc-

tion losses and provides higher efficiency at heavy loads.

Peak efficiency is about the same with either method.

be optional. C1 is usually selected to be in the range of

0.01ꢁF to 0.4ꢀꢁF. This forces R1|| R2 to around 2k to 4k,

reducing error that might have been caused by the sense

pins’ input bias currents.

The first step in designing DCR current sensing is to

determine the DCR of the inductor. Where provided, use

themanufacturer’smaximumvalue, usuallygivenat25°C.

Increase this value to account for the temperature coef-

ficient of resistance, which is approximately 0.47/°C. A

To maintain a good signal-to-noise ratio for the current

sense signal, use a minimum ΔV

of 10mV. For a

SENSE

DCR sensing application, the actual ripple voltage will be

determined by:

conservative value for inductor temperature T is 100°C.

L

V –V

R1•C1 V • f

V_OUT

IN

OUT

ΔV_SENSE

=

•

TheDCRoftheinductorcanalsobemeasuredusingagood

RLC meter, but the DCR tolerance is not always the same

and varies with temperature; consult the manufacturers’

datasheets for detailed information.

IN

Operating Multiple Units in Parallel

The LTC3613’s current mode control architecture makes

it straightforward to parallel multiple units for higher

output current. Figure 13 shows an example circuit of two

LTC3613s placed in parallel to provide 30A at 1.2V from

a 6V to 24V input. The signals at MODE/PLLIN are 180°

out of phase, to reduce stress on the input and output

capacitors.

From the DCR value, V

is calculated as:

SENSE(MAX)

⎡

⎤

⎦

V_SENSE(MAX)=DCR_MAXat 25°C• 1+0.47 T

–25°C

(

)

L(MAX)

⎣

⎡

⎤

• I_OUT(MAX)–ΔI_L/2

⎣

⎦

If V

is within the maximum sense voltage of

SENSE(MAX)

the LTC3613 as programmed by the V

pin (30mV to

RNG

Since the ITH pin voltage determines the cycle-by-cycle

valley inductor current, sharing is achieved by connecting

the ITH pins together. Because the ITH pin is sensitive to

noise, a small 22pF to 4ꢀpF decoupling capacitor should

100mV), thentheRCfilteronlyneedsR1. IfV

is

SENSE(MAX)

higher, then R2 may be used to scale down the maximum

sense voltage so that it falls within range.

3613fa

17

LTC3613

APPLICATIONS INFORMATION

beplacedclosetoeachITHpin. Ifacompensationscheme

is stable on a single phase application, a polyphase ap-

plication with N phases should be compensated as:

The output ripple is highest at maximum input voltage

since ΔI increases with input voltage. Typically, once the

L

ESR requirement for C

has been met, the RMS current

OUT

ratinggenerallyfarexceedsthepeak-to-peakcurrentripple

requirement. The choice of using smaller output capaci-

tance increases the ripple voltage due to the discharging

term but can be compensated for by using capacitors of

very low ESR to maintain the ripple voltage.

C

= N • C

, C

= N • C

and

ITH1

ITH(SINGLE) ITH2

ITH2(SINGLE)

R

= R

/N.

ITH

ITH(SINGLE)

The TRACK/SS pins should be connected together so

that all LTC3613s start up with the same slew rate. The

+

V

pinsofparalleledLTC3613sshouldbeconnected

OSENSE

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, special polymer, aluminum electrolytic and

ceramiccapacitorsareallavailableinsurfacemountpack-

ages. Special polymer capacitors offer very low ESR but

havelowercapacitancedensitythanothertypes.Tantalum

capacitors have the highest capacitance density but it is

important to only use types that have been surge tested

foruseinswitchingpowersupplies.Aluminumelectrolytic

capacitors have significantly higher ESR, but can be used

in cost-sensitive applications provided that consideration

is given to ripple current ratings and long-term reliability.

CeramiccapacitorshaveexcellentlowESRcharacteristics

but can have a high voltage coefficient and audible piezo-

electriceffects.ThehighQofceramiccapacitorswithtrace

inductancecanalsoleadtosignificantringing.Whenusing

ceramic input capacitors, care must be taken to ensure

that ringing from inrush currents and switching does not

pose an overvoltage hazard to the regulator.

together to prevent any false triggering of overvoltage and

short circuit protection. Only one divider is necessary. The

remoteoutputandgroundtracesshouldberoutedtogether

as differential pairs and terminated at the same remote

sensing location (preferably Kelvin connected across the

bulk capacitors at the remote output point). The smaller

valueceramicinputandoutputcapacitors,however,should

be in close proximity to the ICs.

C and C

Selection

IN

OUT

Incontinuousmode,thecurrentintoPV isasquarewave

IN

ofdutycycleV /V .Topreventlargevoltagetransients,

OUT IN

a low ESR input capacitor sized for the maximum RMS

current must be used. The maximum RMS capacitor cur-

rent is given by:

V_OUT

V

V_OUT

IN

I_RMS≅I_OUT(MAX)

•

–1

V

IN

This formula has a maximum at V = 2V , where I

RMS

IN

OUT

Forhighswitchingfrequencies,reducingoutputrippleand

betterEMIfilteringmayrequiresmall-valuecapacitorsthat

have low ESL (and correspondingly higher self resonant

frequencies) to be placed in parallel with larger value

capacitors that have higher ESL. This will ensure good

noise and EMI filtering in the entire frequency spectrum

of interest. Even though ceramic capacitors generally

have good high frequency performance, small ceramic

capacitors may still have to be parallel connected with

large ones to optimize performance.

= I

/2. This simple worst-case condition is com-

OUT(MAX)

monlyusedfordesignbecauseevensignificantdeviations

do not offer much relief. Note that capacitor manufactur-

ers’ ripple current ratings for electrolytic and conductive

polymer capacitors are often based on only 2000 hours of

life. This makes it advisable to further derate the capacitor

or to choose a capacitor rated at a higher temperature

than required.

The selection of C

is primarily determined by the effec-

OUT

tiveseriesresistance, ESR, tominimizevoltageripple. The

outputripple,ΔV ,incontinuousmodeisdeterminedby:

OUT

⎛

⎞

1

ΔV_OUT≤ΔI_LR_ESR

+

⎜

⎝

⎟

8• f•C_OUT

⎠

3613fa

18

LTC3613

APPLICATIONS INFORMATION

Top MOSFET Driver Supply (C , D )

When the voltage applied to EXTV pin rises above 4.6V,

CC

B

the INTV LDO is turned off and the EXTV is connected

CC

Anexternalbootstrapcapacitor,C ,connectedtotheBOOST

B

to INTV with an internal switch. This switch remains on

CC

pinsuppliesthegatedrivevoltageforthetopsideMOSFET.

as long as the voltage applied to EXTV remains above

CC

This capacitor is charged through diode D from INTV

B

CC

4.4V. Using the EXTV allows the MOSFET driver and

CC

when the switch node is low. When the top MOSFET turns

control power to be derived from the LTC3613’s switching

regulator output during normal operation and from the

LDO when the output is out of regulation (e.g., start-up,

on, the switch node rises to V and the BOOST pin rises to

IN

approximatelyPV +INTV .Theboostcapacitorneedsto

IN

CC

storeapproximately100timesthegatechargerequiredby

thetopMOSFET.Inmostapplicationsa0.1ꢁFto0.4ꢀꢁF,X5R

orXꢀRdielectriccapacitorisadequate.Itisrecommended

that the BOOST capacitor be no larger than 107 of the

short circuit). If more than 50mA

current is required

RMS

through EXTV , then an external Schottky diode can be

CC

added between the EXTV and INTV pins. Do not apply

CC

more than 6V to the EXTV pin and make sure that this

CC

INTV capacitor, C , to ensure that the C can supply

CC

VCC

external voltage source is less than SV .

IN

theupperMOSFETgatechargeandBOOSTcapacitorunder

all operating conditions. Variable frequency in response

to load steps offers superior transient performance but

requires higher instantaneous gate drive. Gate charge

demands are greatest in high frequency low duty factor

applications under high dI/dt load steps and at start-up.

Significant efficiency and thermal gains can be realized

by powering INTV from the switching regulator output,

CC

since the V current resulting from the driver and control

IN

currentswillbescaledbyafactorof(DutyCycle)/(Switcher

Efficiency).

In order to minimize SW node ringing and EMI, connect a

5Ω to 10Ω resistor in series with the BOOST pin. Make the

The following list summarizes the four possible connec-

tions for EXTV :

CC

C andD connectionsontheothersideoftheresistor.This

B

1. EXTV leftopen(orgrounded).ThiswillcauseINTV

CC

series resistor helps to slow down the SW node rise time,

limitingthehighdI/dtcurrentthroughthetopMOSFETthat

causes SW node ringing.

to be powered from the internal 5.3V LDO resulting

in an efficiency penalty of up to 107 at high input

voltages.

INTV Regulator and EXTV Power

2. EXTV connecteddirectlytoswitchingregulatoroutput

CC

V

> 4.6V. This provides the highest efficiency.

OUT

TheLTC3613featuresaPMOSlowdropoutlinearregulator

(LDO)thatsuppliespowertoINTV fromtheSV supply.

3. EXTV connected to an external supply. If a 4.6V or

CC

IN

CC

INTV powers much of the LTC3613’s internal circuitry.

greater external supply is available, it may be used to

CC

The LDO regulates the voltage at the INTV pin to 5.3V.

power EXTV provided that the external supply is suf-

CC

ficient enough for MOSFET gate drive requirements.

The LDO can supply a maximum current of 50mA

and

RMS

must be bypassed to ground with a minimum of 4.ꢀꢁF

ceramic capacitor. Good bypassing is needed to supply

thehightransientcurrentsrequiredbythepowerMOSFET

gate drivers.

4. EXTV connectedtoanoutput-derivedboostnetwork.

CC

For 3.3V and other low voltage converters, efficiency

gains can still be realized by connecting EXTV to an

CC

output-derivedvoltagethathasbeenboostedtogreater

than 4.6V.

3613fa

19

LTC3613

APPLICATIONS INFORMATION

For applications where the main input power is less than

Soft-Start and Tracking

5.3V, tie the V and INTV pins together and tie the

IN

CC

The LTC3613 has the ability to either soft-start by itself

with a capacitor or track the output of an external supply.

Soft-start or tracking features are achieved not by limiting

the maximum output current of the switching regulator

but by controlling the regulator’s output voltage according

to the ramp rate on the TRACK/SS pin.

combined pins to the PV input with an optional 1Ω or

IN

2.2Ω resistor as shown in Figure 5 to minimize the voltage

drop caused by the gate charge current. This will override

the INTV LDO and will prevent INTV from dropping

CC

too low due to the dropout voltage.

When configured to soft-start by itself, a capacitor should

be connected to the TRACK/SS pin. TRACK/SS is pulled

low until the RUN pin voltage exceeds 1.2V and UVLO is

released, atwhichpointaninternalcurrentof1ꢁAcharges

LTC3613

V

PV

IN

C

IN

INTV

CC

R

VIN

the soft-start capacitor, C , connected to TRACK/SS.

SS

SV

IN

Current foldback is disabled during this phase to ensure

smooth soft-start or tracking. The soft-start or tracking

range is defined to be the voltage range from 0V to 0.6V

on the TRACK/SS pin. The total soft-start time can be

calculated as:

C

VCC

3613 F05

Figure 5. Setup for V_IN≤ 5V

V Undervoltage Lockout (UVLO)

IN

C_SS

t_SOFTSTART=0.6V•

1μA

The LTC3613 has two functions that help protect the con-

trollerincaseofinputundervoltageconditions.Aprecision

UVLOcomparatorconstantlymonitorstheINTV voltage

CC

When the LTC3613 is configured to track another supply,

a voltage divider can be used from the tracking supply to

the TRACK/SS pin to scale the ramp rate appropriately.

Two common implementations of tracking as shown in

Figure 6 are coincident and ratiometric. For coincident

tracking, make the divider ratio from the external supply

the same as the divider ratio for the differential feedback

voltage. Ratiometric tracking could be achieved by using

a different ratio than the differential feedback (Figure ꢀ).

Note that the small soft-start capacitor charging current is

alwaysflowing,producingasmalloffseterror.Tominimize

this error, select the tracking resistive divider values to be

small enough to make this offset error negligible.

to ensure that an adequate gate-drive voltage is present.

The comparator enables UVLO and locks out the switch-

ing action until INTV rises above 4.2V. Once UVLO is

CC

released, the comparator does not retrigger UVLO until

INTV falls below 3.65V. This hysteresis prevents oscil-

CC

lations when there are disturbances on INTV .

CC

Another way to detect an undervoltage condition is to

monitortheV supply.BecausetheRUNpinhasaprecision

IN

turn-onvoltageof1.2V, onecanusearesistordividerfrom

V toturnontheICwhenV ishighenough. TheRUNpin

IN

hasbiascurrentsthatdependontheRUNvoltageaswellas

SV voltage. These bias currents should be taken into ac-

IN

countwhendesigningthevoltagedividerandUVLOcircuit

to prevent faulty conditions. Generally for RUN < 3V a bias

current of 1.3ꢁA flows out of the RUN pin, and for RUN >

3V, correspondingly increasing current flows into the pin,

reachingabout35ꢁAforRUN=6V.

3613fa

20

LTC3613

APPLICATIONS INFORMATION

EXTERNAL

SUPPLY

EXTERNAL

SUPPLY

V

OUT

3613 F06

TIME

Ratiometric Tracking

Coincident Tracking

Figure 6. Two Different Modes of Output Tracking

EXT. V

V

EXT. V

V

OUT

R

R1

R

FB2

FB1

FB2

R2

R1+ R2 EXT. V

R2

0.6V

TO

TRACK/SS

TO

TRACK/SS

+

–

+

–

≥

TO V

OSNS

FB1

TO V

3613 F0ꢀ

Coincident Tracking Setup

Ratiometric Tracking Setup

Figure 7. Setup for Coincident and Ratiometric Tracking

Phase and Frequency Synchronization

An internal PLL system adjusts this on-time dynamically

in order to maintain phase and frequency lock with the

external clock. The LTC3613 will maintain phase and fre-

For applications that require better control of EMI and

switching noise or have special synchronization needs,

the LTC3613 can phase and frequency synchronize the

turn-on of the switching cycle to an external clock signal

applied to the MODE/PLLIN pin. The applied clock signal

needs to be within 307 of the RT pin programmed free-

running frequency to assure proper frequency and phase

quency lock under steady-state conditions for V , V

IN OUT

and load current.

As shown in the previous equation, the on-time is a

function of the switching regulator’s output. This output

is measured by the V

pin and is used to calculate the

OUT

lock.TheclocksignallevelsshouldgenerallycomplytoV

required on-time. Therefore, simply connecting V

to

IH

OUT

> 2V and V < 0.5V. The MODE/PLLIN pin has an internal

the regulator’s local output point is preferable for most

applications. However, there could be applications where

the internally calculated on-time differs significantly from

the real on-time required by the application. For example,

if there are differences between the local output point and

theremotelyregulatedoutputpointduetolinelosses,then

the internally calculated on-time will be inaccurate. Lower

efficiencies in the switching regulator can also cause the

realon-timetobesignificantlydifferentfromtheinternally

IL

600k pull-down resistor to ensure pulse-skipping mode

if the pin is left floating.

The LTC3613 uses the voltages on SV and V

pins as

IN

OUT

well as the RT programmed frequency to determine the

steady-state on-time as follows:

V_OUT

t_ON

≈

V •f

IN

3613fa

21

LTC3613

APPLICATIONS INFORMATION

calculated on-time (see Efficiency Considerations). For

During dynamic transient conditions either in the line or

load (e.g., load step or release), the LTC3613 may lose

phase and frequency lock in the process of achieving

faster transient response. For large slew rates (e.g., 10A/

μs), phase and frequency lock will be lost (see Figure 8)

until the system returns back to a steady-state condition

at which point the device will resume frequency lock and

eventually achieve phase lock to the external clock. For

relatively small slew rates (10A/s), phase and frequency

lock can still be maintained.

these circumstances, the voltage on the V

pin can

OUT

be programmed with a resistive divider from INTV or

CC

from the regulator’s output itself. Note that there is a 500k

nominal resistance looking into the V

pin.

OUT

The PLL adjusted on-time achieved after phase locking is

the steady-state on-time required by the switching regula-

tor, and if the V

programmed on-time is substantially

OUT

equal to this steady-state on-time, then the PLL system

does not have to use its 307 frequency lock range for

systematiccorrections.Insteadthelockrangecanbeused

tocorrectforcomponentvariationsorotheroperatingpoint

For light loading conditions, the phase and frequency

synchronization will be active if there is a clock input ap-

plied. If there is no clock input during light loading, then

theswitchingfrequencyisbasedonwhattheMODE/PLLIN

conditions. If needed, the V

pin can be programmed to

OUT

achievethesteady-stateon-timeasrequiredbytheapplica-

tion and therefore maintain constant frequency operation.

pin is tied to. When MODE/PLLIN is tied to INTV , the

CC

LTC3613 will operate in forced continuous mode at the RT

programmedfree-runningfrequency.WhenMODE/PLLIN

pin is tied to signal ground, the LTC3613 will operate in

pulse-skipping discontinuous conduction mode for light

loading and will switch to continuous conduction (at the

free-running frequency) for normal and heavy loads.

If the application requires very low on-times approaching

minimum on-time, the PLL system may not be able to

maintain a 307 synchronization range. In fact, there is

a possibility of losing phase/frequency lock at minimum

on-time, and definitely losing phase/frequency lock for

applications requiring less than minimum on-time. This

is discussed further under Minimum On-Time, Minimum

Off-Time and Dropout Operation.

I

LOAD

CLOCK

INPUT

PHASE LOCKED

ESTABLISHES

FREQUENCY

LOCK SOON

ESTABLISHES

PHASE LOCK

AFTER ~600μs

LOSES PHASE

LOCK DUE TO

FAST LOAD

RELEASE

ESTABLISHES

FREQUENCY

LOCK SOON

LOSES PHASE

LOCK DUE

TO FAST

LOAD STEP

SW

V

OUT

3613 F08

Figure 8. Phase and Frequency Locking Behavior During Transient Load Conditions

3613fa

22

LTC3613

APPLICATIONS INFORMATION

Minimum On-Time, Minimum Off-Time

and Dropout Operation

where t

is the minimum off-time of the switching

OFF(MIN)

regulator. Reducing the operating frequency alleviates the

maximumdutycycleconstraint.Ifthemaximumdutycycle

is reached, due to a drooping input voltage for example,

then the output will drop out of regulation. The minimum

input voltage to avoid dropout is:

The minimum on-time is the smallest duration of time in

which the LTC3613 can keep its top power MOSFET in its

on state. This minimum on-time is 65ns for the LTC3613

and is achieved when the V

pin is tied to its minimum

OUT

V_OUT

D_MAX

value of 0.6V while the PV is tied to its maximum value

IN

V

=

IN(MIN)

of 24V. For larger values of V

or smaller values of

OUT

PV , the minimum on-time achievable will be longer than

IN

At the onset of dropout, there is a region of PV about

IN

65ns. The minimum on-time will have a dependency on

the operating conditions of the switching regulator, but is

intended to be smaller for high step-down ratio applica-

tions that will require low on-times.

500mV that generates two discrete off-times, one being

the minimum off-time and the other being an off-time that

is about 40ns to 60ns larger than the minimum off-time.

This secondary off-time is due to the longer delay in trip-

ping the internal current comparator. The two off-times

average out to the required duty cycle to keep the output

in regulation with the output ripple remaining the same.

However, there is higher SW node jitter, especially appar-

ent when synchronized to an external clock. Depending

on the application, this may not be of critical importance.

Incontinuousmodeoperation, theminimumon-timelimit

imposes a minimum duty cycle of:

D

MIN

= f • t

ON(MIN)

where t

is the minimum on-time for the switching

ON(MIN)

regulator. As the equation shows, reducing the operating

frequencywillalleviatetheminimumdutycycleconstraint.

Fault Conditions: Current Limiting and Overvoltage

If the application requires a smaller than minimum duty

cycle, the output voltage will still remain in regulation, but

theswitchingfrequencywilldecreasefromitsprogrammed

valueorlosefrequencysynchronizationifusinganexternal

clock. Depending on the application, this may not be of

critical importance.

The maximum inductor current is inherently limited in a

current mode controller by the maximum sense voltage.

In the LTC3613, the maximum sense voltage is controlled

by the voltage on the V

pin. With valley current mode

RNG

control, the maximum sense voltage and the sense re-

sistance determine the maximum allowed inductor valley

current. The corresponding output current limit is:

The minimum off-time is the smallest duration of time

that the top power MOSFET can be turned off and then

immediately turned back on. The minimum off-time that

the LTC3613 can achieve is 105ns.

V

1

I_LIMIT

=

^SENSE(MAX)+ • ΔI_L

R_SENSE

2

The minimum off-time limit imposes a maximum duty

cycle of:

The current limit value should be checked to ensure that

> I . The current limit value should

I

LIMIT(MIN)

OUT(MAX)

be greater than the inductor current required to produce

maximum output power at the worst-case efficiency.

D

MAX

= 1 – f • t

OFF(MIN)

Worst-case efficiency typically occurs at the highest PV

and highest ambient temperature.

IN

3613fa

23

LTC3613

APPLICATIONS INFORMATION

To further limit current in the event of a short circuit to

ground, the LTC3613 includes foldback current limiting.

If the output fails by more than 507, then the maximum

sensevoltageisprogressivelyloweredtoaboutone-fourth

of its full value.

time of 1ꢁs to 10ꢁs will produce output voltage and ITH

pin waveforms that will give a sense of the overall loop

stability without breaking the feedback loop. The general

goal of OPTI-LOOP compensation is to realize a fast but

stable ITH response with minimal output droop due to

the load step. For a detailed explanation of OPTI-LOOP

compensation, refer to Application Note ꢀ6.

If the output exceeds ꢀ.57 of the programmed value,

then it is considered as an overvoltage (OV) condition.

In such a case, the top MOSFET is immediately turned

off and the bottom MOSFET is turned on indefinitely until

the OV condition is removed. Current limiting is not ac-

tive during an OV. If the output returns to a nominal level,

then normal operation resumes. If the OV persists a long

time, the current through the inductor could exceed its

maximum rating.

Switching regulators take several cycles to respond to a

step in load current. When a load step occurs, V

im-

OUT

•ESR,where

mediatelyshiftsbyanamountequaltoΔI

LOAD

ESR is the effective series resistance of C . ΔI

also

OUT

LOAD

beginstochargeordischargeC ,generatingafeedback

OUT

error signal used by the regulator to return V

to its

can

OUT

steady-state value. During this recovery time, V

OUT

be monitored for overshoot or ringing that would indicate

a stability problem.

OPTI-LOOP Compensation

OPTI-LOOP compensation, through the availability of the

ITH pin, allows the transient response to be optimized for

a wide range of loads and output capacitors. The ITH pin

not only allows optimization of the control loop behavior

butalsoprovidesatestpointforthestep-downregulator’s

DC-coupledandAC-filteredclosed-loopresponse.TheDC

step,risetimeandsettlingatthistestpointtrulyreflectsthe

closed-loop response. Assuming a predominantly second

ordersystem, phasemarginand/ordampingfactorcanbe

estimated using the percentage of overshoot seen at this

pin. The bandwidth can also be estimated by examining

the rise time at this pin.

ConnectingaresistiveloadinserieswithapowerMOSFET,

then placing the two directly across the output capacitor

and driving the gate with an appropriate signal generator

is a practical way to produce a realistic load-step condi-

tion. The initial output voltage step resulting from the step

change in output current may not be within the bandwidth

of the feedback loop, so this signal cannot be used to

determine phase margin. This is why it is better to look

at the ITH pin signal which is in the feedback loop and

is the filtered and compensated feedback loop response.

ThegainoftheloopincreaseswithR andthebandwidth

ITH

of the loop increases with decreasing C

. If R is

ITH1

ITH

TheITHseriesR -C

filtersetsthedominantpole-zero

increased by the same factor that C

is decreased, the

ITH ITH1

ITH1

loop compensation. Additionally, a small capacitor placed

from the ITH pin to SGND, C , may be required to at-

zero frequency will be kept the same, thereby keeping the

phase the same in the most critical frequency range of the

ITH2

tenuate high frequency noise. The values can be modified

to optimize transient response once the final PCB layout

is done and the particular output capacitor type and value

have been determined. The output capacitors need to be

selectedbecausetheirvarioustypesandvaluesdetermine

theloopfeedbackfactorgainandphase. Anoutputcurrent

pulse of 207 to 1007 of full load current having a rise

feedbackloop.Inaddition,afeedforwardcapacitor,C ,can

FF

beaddedtoimprovethehighfrequencyresponse,asshown

in Figure 1. Capacitor C provides phase lead by creating

FF

a high frequency zero with R which improves the phase

FB2

margin. The output voltage settling behavior is related to

thestabilityoftheclosed-loopsystemandwilldemonstrate

overall performance of the step-down regulator.

3613fa

24

LTC3613

APPLICATIONS INFORMATION

Insomeapplications,amoreseveretransientcanbecaused

by switching in loads with large (>10ꢁF) input capacitors.

If the switch connecting the load has low resistance and

is driven quickly, then the discharged input capacitors are

3. INTV current. This is the sum of the MOSFET driver

CC

and control currents. The MOSFET driver current re-

sults from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge, dQ, moves

effectivelyputinparallelwithC , causingarapiddropin

OUT

V

OUT

. No regulator can deliver enough current to prevent

from INTV to ground. The resulting dQ/dt is a current

CC

this problem. The solution is to limit the turn-on speed of

the load switch driver. A Hot Swap™ controller is designed

specifically for this purpose and usually incorporates cur-

rent limiting, short-circuit protection and soft starting.

out of INTV that is typically much larger than the

CC

controller I current.

Q

Supplying INTV power through EXTV could save

CC

several points of efficiency, especially for high V ap-

IN

plications. Connecting EXTV to an output-derived

CC

Efficiency Considerations

source will scale the V current required for the driver

IN

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 1007.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

and controller circuits by a factor of Duty Cycle/Effi-

ciency. For example, in a 20V to 5V application, 10mA

ofINTV currentresultsinapproximately2.5mAofV

CC

IN

current. This reduces the mid-current loss from 107

or more (if the driver was powered directly from V )

IN

to only a few percent.

7Efficiency = 1007 – (L1 + L2 + L3 + ...)

4. C loss. The input capacitor has the difficult job of

IN

filtering the large RMS input current to the regulator. It

where L1, L2, etc. are the individual losses as a percent-

age of input power. Although all dissipative elements in

the circuit produce losses, four main sources account for

most of the losses:

2

must have a very low ESR to minimize the AC I R loss

and sufficient capacitance to prevent the RMS current

from causing additional upstream losses in cabling,

fuses or batteries.

2

1. I R losses. These arise from the resistances of the

Other losses, which include the C

ESR loss, bottom

OUT

MOSFETs, inductor and PC board traces and cause

the efficiency to drop at high output currents. In

continuous mode the average output current flows

though the inductor L, but is chopped between the

top and bottom MOSFETs.

MOSFET reverse-recovery loss and inductor core loss

generally account for less than 27 additional loss.

Whenmakingadjustmentstoimproveefficiency, theinput

current is the best indicator of changes in efficiency. If you

make a change and the input current decreases, then the

efficiency has increased. If there is no change in input

current there is no change in efficiency.

2. Transition loss. This loss arises from the brief amount

of time the top MOSFET spends in the saturated region

during switch node transitions. It depends upon the

inputvoltage,loadcurrent,driverstrengthandMOSFET

capacitance,amongotherfactors.Thelossissignificant

at input voltages above 20V.

Power losses in the switching regulator will reflect as a

longer than ideal on-time. This efficiency accounted on-

time in continuous mode can be calculated as:

t_ON(IDEAL)

t_ON(REAL)

≈

Efficiency

3613fa

25

LTC3613

APPLICATIONS INFORMATION

Design Example

Theminimumon-timeoccursformaximumV andshould

IN

be greater than 65ns, which is the best that the LTC3613

Considerastep-downconverterwithV =6Vto24V, V

IN

OUT

can achieve. The minimum on-time for this application is:

= 1.2V, I

= 15A, and f = 350kHz (see Figure 9).

OUT(MAX)

V_OUT

_IN(MAX)• f 24V•350kHz

1.2V

The regulated output voltage is determined by:

t_ON(MIN)

=

≈143ns

V

⎛

⎞

⎟

⎠

R_FB2

R_FB1

V_OUT=0.6V• 1+

⎜

⎝

Set the inductor value to give 407 ripple current at maxi-

mum V :

IN

+

–

Using a 20k resistor from V

feedback resistor is also 20k.

to V

, the top

OSNS

1.2V

350kHz•407•15A

1.2V

24V

⎛

⎞

L=

• 1–

≈0.54μH

⎜

⎟

⎠

⎝

The frequency is programmed by:

Select 0.56ꢁH, which is the nearest standard value.

41550

f kHz

41550

350

R kΩ =

–2.2=

–2.2≈116.5k

[

]

T

[

]

Select the nearest standard value of 115k.

SV

PV

IN

INTV

CC

R

V

IN

PGD

100k

6V TO 24V

+

C

82μF

25V

IN1

C

PGOOD

LTC3613

V

OUT

IN2

10μF

R

DIV1

100

90

80

ꢀ0

60

50

40

30

20

10

0

52.3k

–

SENSE

PULSE-SKIPPING

MODE

V

RNG

C

R

DCR

0.1μF

R

3.09k

DIV2

+

10k

SENSE

RUN

350kHz

L1

0.56μH

FORCED

CONTINUOUS

MODE

MODE/PLLIN

EXTV

CC

V

OUT

1.2V

15A

SW

C

0.1μF

C

B

SS

0.1μF

BOOST

TRACK/SS

ITH

R

FB2

D

B

C

ITH1

C

OUT1

20k

C

+

OUT2

INTV

CC

INTV

VCC

R

220pF

CC

ITH

330μF

100μF

28k

C

4.ꢀμF

2.5V

×2

R

V

= 12V

FB1

IN

OUT

20k

= 1.2V

C

100pF

ITH2

0.1

1

10

100

PGND

+

LOAD CURRENT (A)

R

T

3613 F10a

115k

V

RT

SGND

OSNS

–

OSNS

3613 F10

C

: SANYO 25SVPD82M

OUT1

D : CENTRAL CMDSH-3

B

L1: VISHAY IHLP4040DZ-056μH

IN1

: SANYO 2R5TPE330M9

Figure 9. 1.2V, 15A, 350kHz Step-Down Converter

3613fa

26

LTC3613

APPLICATIONS INFORMATION

The resulting maximum ripple current is:

However, a 0A to 10A load step will cause an output

change of up to:

1.2V

350kHz•0.56μH

1.2V

24V

⎛

⎞

ΔI_L=

• 1–

≈5.8A

⎜

⎟

⎠

ΔV

= ΔI

• ESR = (10A)(4.5mΩ) = 45mV

⎝

OUT(STEP)

LOAD

Optional 100ꢁF ceramic output capacitors are included to

minimize the effect of ESR and ESL in the output ripple

and to improve load step response.

Often in high power applications, DCR current sensing is

preferred over R in order to maximize efficiency. In

SENSE

order to determine the DCR filter values, first the induc-

tor manufacturer has to be chosen. For this design, the

Vishay IHLP-4040DZ-01 model is chosen with a value of

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the LTC3613.

0.56ꢁH and DCR

=1.8mΩ. This implies that:

MAX

V

=DCR

at25°C•[1+0.47(T

OUT(MAX)

SENSE(MAX)

MAX L(MAX)

– 25°C)] • [I

– ΔI /2]

L

• Multilayer boards with dedicated ground layers are

preferable for reduced noise and for heat sinking pur-

= 1.8mΩ • [1 + 0.47 (100°C – 25°C)] •

[15A – 5.8A/2]

poses. Use wide rails and/or entire planes for V , V

IN OUT

and PGND nodes for good filtering and minimal copper

loss. Flood unused areas of all layers with copper for

better heat sinking.

≈ 28.3mV

The maximum sense voltage is within the range that

LTC3613canhandlewithoutanyadditionalscaling.There-

fore, the DCR filter consists of a simple RC filter across

the inductor. If the C is chosen to be 0.1μF, then the R can

be calculated as:

• Keep signal and power grounds separate except at the

point where they are shorted together. Short signal and

power ground together only at a single point with a nar-

row PCB trace (or single via in a multilayer board). All

powertraincomponentsshouldbereferencedtopower

L

0.56μH

R_DCR

=

≈3.11k

DCR_MAX•C_DCR1.8mΩ•0.1μF

ground and all small-signal components (e.g., C

,

ITH1

R , C etc.) should be referenced to signal ground.

T

SS

The closest standard value is 3.09k.

• PlaceC ,inductor,senseresistor(ifused),andprimary

IN

The resulting value of V

factor is:

with a 507 design margin

RNG

C

OUT

capacitors close together in one compact area.

The SW node should be compact but be large enough

to handle the inductor currents without large copper

V

RNG

= V

/0.05 • MF

SENSE(MAX)

losses. Connect PV as close as possible to the (+)

IN

= 28.3mV/0.05 • 1.5 ≈ 850mV

To generate the V voltage, connect a resistive divider

plate of C capacitor(s) that provides the bulk of the

IN

AC current (these are normally the ceramic capaci-

RNG

from INTV to SGND with R

= 52.3k and R

= 10k.

tors), and connect PGND as close as possible to the

CC

DIV1

DIV2

(–) terminal of the same C capacitor(s). The high dI/

IN

Select C to give an RMS current rating greater than ꢀA

at ꢀ5°C. The output capacitor C

ESR of 4.5mΩ to minimize output voltage changes due to

inductor ripple current and load steps. The output voltage

ripple is given as:

IN

dt loop formed by C , the top MOSFET, and the bot-

IN

is chosen for a low

OUT

tom MOSFET should have short leads and PCB trace

lengths to minimize high frequency EMI and voltage

stress from inductive ringing. The (–) terminal of the

primary C

capacitor(s) which filter the bulk of the

OUT

ΔV

= ΔI

• ESR = (5.8A)(4.5mΩ)

OUT(RIPPLE)

L(MAX)

≈ 26mV

inductor ripple current (these are normally the ceramic

capacitors) should also be connected close to the (–)

terminal of C .

IN

3613fa

27

LTC3613

APPLICATIONS INFORMATION

• Place the BOOST, PV , SW, and PGND pins facing the

• PlacetheceramicC capacitorascloseaspossibleto

VCC

IN

power train components. Keep high dV/dt signals on

BOOSTandSWawayfromsensitivesmall-signaltraces

and components.

the INTV and PGND pins. Likewise, the C capacitor

CC B

should be as close as possible to BOOST and SW pins.

Thesecapacitorsprovidethegatechargingcurrentsfor

the onboard power MOSFETs.

•

For R_SENSEcurrent sensing, place the sense resistor

close to the inductor on the output side. Use a Kelvin

(4-wire) connection across the sense resistor and

route the traces together as a differential pair. RC filter

the differential sense signal close to SENSE⁺/SENSE^–

pins, placing the filter capacitor as close as possible

to the pins. For DCR sensing, Kelvin connect across

the inductor and place the DCR sensing resistor closer

to the SW node and further away from the SENSE⁺/

SENSE^–pins. Place the DCR capacitor close to the

SENSE⁺/SENSE^–pins.

• Placesmall-signalcomponentsasclosetotheirrespec-

tive pins as possible. This minimizes the possibility of

PCB noise coupling into these pins. Give priority to

SENSE⁺/SENSE^–, ITH, RT and V

+

–

V

/V

,

OSNS

OSNS RNG

pins.Usesufficientisolationwhenroutingaclocksignal

into MODE/PLLIN pin so that the clock does not couple

into sensitive small-signal pins.

• Filter the SV input to the LTC3613 with a simple RC

IN

filter close to the pin. The RC filter should be referenced

to signal ground.

• Place the resistive feedback divider R

as close as

FB1/2

+

–

possible to V

/V

pins and route the remote

OSNS

output and ground traces together as a differential

pair and terminate as close to the regulation point as

possible(preferablyKelvinconnectacrossthecapacitor

at the remote output point).

3613fa

28

LTC3613

APPLICATIONS INFORMATION

PV

IN

INTV

R

VIN

2.2Ω

CC

V

IN

SV

IN

4.5V TO 24V

+

C

82μF

25V

IN2

IN1

C

VIN

22μF

R

LTC3613

0.1μF

PGD

×2

100k

V

PGOOD

OUT

R

F2

10Ω

–

SENSE

C

F

R

10Ω

F1

1000pF

+

RUN

R

L1

0.4ꢀμH

SENSE

V

RNG

1.5mΩ

V

1.5V

15A

OUT

MODE/PLLIN

EXTV

SW

C

B

CC

0.1μF

C

R

OUT2

FB2

C

0.1μF

100μF

SS

BOOST

15k

×2

D

B

TRACK/SS

C

OUT1

+

R

C

4ꢀpF

21k

FB1

330μF

ITH2

10k

INTV

CC

INTV

2.5V

×2

CC

C

VCC

4.ꢀμF

C

2ꢀ0pF

ITH1

R

ITH

PGND

+

ITH

R

T

115k

RT

SGND

V

OSNS

–

3833 F11

C

: SANYO 25SVPD82M

OUT1

D : CENTRAL CMDSH-3

B

L1: COILTRONICS FP1109-R4ꢀ

IN1

: SANYO 2R5TPE330M9

Efficiency

100

PULSE-SKIPPING

MODE

90

80

ꢀ0

60

50

40

FORCED

CONTINUOUS

MODE

V

= 12V

IN

OUT

= 1.5V

0.1

1

10

100

LOAD CURRENT (A)

3613 F11a

Figure 10. 1.5V, 15A, 350kHz High Current Step-Down Converter

3613fa

29

LTC3613

TYPICAL APPLICATIONS

PV

SV

IN

R

VIN

2.2Ω

V

IN

ꢀV TO 24V

C

+

C

IN2

C

VIN

IN1

INTV

CC

R

10μF

0.1μF

PGD

EXTV

100μF

50V

CC

100k

×3

PGOOD

RUN

V

OUT

–

SENSE

30.9k

10k

C

0.1μF

R

DCR

8.25k

V

+

RNG

L1

4.ꢀμH

C

SS

V

5V

8A

LTC3613

OUT

0.1μF

SW

C

B

TRACK/SS

R

B

0.1μF

C

ITH1

10Ω

R

1000pF

ITH

BOOST

R

FB2

49.9k

C

D

OUT1

14ꢀk

B

C

ITH

+

OUT2

330μF

6.3V

×2

100μF

R

INTV

T

CC

×2

205k

R

FB1

C

RT

VCC

4.ꢀμF

20k

MODE/PLLIN

PGND

+

OSNS

–

V

SGND

OSNS

3613 TA02

C

: NICHICON UCJ1H101MCL1GS

OUT1

D : DIODES INC. SDM10K45

B

L1: COILCRAFT XAL1010-4ꢀ2ME

IN1

: SANYO 6TPE330MIL

Efficiency

100

V

= 12V

OUT

IN

= 5V

95

90

85

80

ꢀ5

ꢀ0

FORCED

CONTINUOUS

MODE

PULSE-SKIPPING

MODE

V

= 12V

OUT

IN

= 5V

0.01

0.1

1

10

LOAD CURRENT (A)

3613 TA03

Figure 11. 5V, 8A, 200kHz High Efficiency Step-Down Converter

3613fa

30

LTC3613

TYPICAL APPLICATIONS

PV

SV

IN

R

VIN

2.2Ω

V

IN

INTV

CC

R

4.5V TO 14V

+

C

82μF

25V

VIN

IN2

IN1

PGD

LTC3613

PGOOD

0.1μF

10μF

100k

×3

V

OUT

–

R

10Ω

F2

MODE/PLLIN

V

SENSE

RNG

R

10Ω

C

F1

F

1000pF

+

RUN

C

SS

R

L1

1μH

SENSE

0.1μF

3mΩ

V

0.6V

10A

OUT

SW

TRACK/SS

C

OUT1

ITH1

4ꢀ0pF

B

+

330μF

2.5V

×2

R

1ꢀ.4k

0.1μF

ITH

BOOST

ITH

D

B

R

T

205k

INTV

CC

INTV

CC

VCC

4.ꢀμF

C

OUT2

RT

100μF

×2

EXTV

PGND

+

CC

V

SGND

OSNS

–

V

OSNS

3613 TA04

C

: SANYO 25SVPD82M

OUT

D : DIODES INC. SDM10K45

B

L1: IHLP-2525EZERR82M01

IN1

: SANYO 2R5TPE330M9

Efficiency

100

90

80

ꢀ0

60

50

40

30

20

10

0

PULSE-SKIPPING

MODE

FORCED

CONTINUOUS

MODE

V

= 12V

IN

OUT

= 0.6V

0.01

10

0.10

1

LOAD CURRENT (A)

3613 TA05

Figure 12. 0.6V, 10A, 200kHz Low Output Voltage Step-Down Converter

3613fa

31

LTC3613

TYPICAL APPLICATIONS

INTV

CC

R

V

IN

6V TO 24V

PGD

V

IN

100k

+

C

82μF

25V

IN1

V

C

PGOOD

LTC3613

OUT

IN2

10μF

R

DIV1

56.2k

–

SENSE

V

RNG

C

DCR

0.1μF

R

DIV2

+

10k

SENSE

RUN

350kHz

MODE/PLLIN

BOOST

SW

EXTV

CC

C

B

C

SS

0.4ꢀμH

2mΩ

0.1μF

TRACK/SS

ITH

D

B

C

ITH1

C

OUT2

INTV

CC

INTV

CC

VCC

R

330pF

ITH

100μF

10k

C

4.ꢀμF

×2

R

FB2

C

4ꢀpF

ITH2

20k

R

PGND

+

FB1

R

T

20k

115k

V

OSNS

RT

SGND

–

V

1.2V

30A

OUT

C

OUT1

+

330μF

2.5V

×4

V

IN

+

IN2

C

82μF

25V

IN1

PGOOD

V

C

OUT

10μF

LTC3613

–

SENSE

V

RNG

C

DCR

0.1μF

+

RUN

SENSE

350kHz

(θ → θ = 180° OUT OF PHASE)

MODE/PLLIN

1

2

BOOST

SW

EXTV

CC

C

B

0.4ꢀμH

2mΩ

0.1μF

TRACK/SS

ITH

D

B

C

OUT2

INTV

CC

INTV

CC

4ꢀpF

100μF

×2

C

4.ꢀμF

VCC

PGND

+

R

T

115k

V

OSNS

RT

SGND

–

OSNS

C

: SANYO 25SVPD82M

OUT1

D : CENTRAL CMDSH-3

B

L1: COILTRONICS FP1109-R4ꢀ

3613 TA12

IN1

: SANYO 2R5TPE330M9

Figure 13. 2 Phase, 1.2V, 30A, 350kHz Step-Down Converter

3613fa

32

LTC3613

TYPICAL APPLICATIONS

Efficiency

100

V

= 12V

IN

OUT

90

80

ꢀ0

60

50

40

= 1.2V

FORCED

CONTINUOUS

MODE

30

20

10

0

0.1

1

10

100

LOAD CURRENT (A)

3613 TA013

Transient Response

V

OUT(AC)

100mV/DIV

I

LOAD

10A/DIV

3613 TA14

20μs/DIV

LOAD STEP = 0A TO 30A

= 12V

V

IN

3613fa

33

LTC3613

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

WKH Package

56-Lead QFN Multipad (7mm × 9mm)

(Reference LTC DWG # 05-08-1870 Rev Ø)

SEATING PLANE

A

2.63 REF

2.90 REF

0.50 BSC

0.00 – 0.05

7.00

BSC

PIN 1 ID

3.82 REF

45

56

B

PAD 1

CORNER

3

44

1

4

1.97

0.10

3.15 0.10

4.06 0.10

4.76 0.10

9.00

BSC

0.95

REF

1.50 REF

NX b

12

2.25 0.10

4.27 0.10

16

29

0.58 0.05

0.40 0.05

28

19

17

0.25 0.05

aaa C 2x

TOP VIEW

0.90 0.10

1.35

0.05

1.78

REF

NX

0.08 C

6

// ccc C

7.50 0.05

BOTTOM VIEW

(BOTTOM METALLIZATION DETAILS)

5

MLP56 QFN REV Ø 0310

2.90 REF

2.63 REF

0.50 BSC

NOTE:

PIN 1

1. DIMENSIONING AND TOLERANCING CONFORM TO ASME Y14.5M-1994

2. ALL DIMENSIONS ARE IN MILLIMETERS, ANGLES ARE IN DEGREES (°)

3

4

THE LOCATION OF THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING

CONVENTION CONFORMS TO JEDEC PUBLICATION 95 SPP-002

3.82 REF

4.06 0.05

3.82 REF

1.97

0.05

3.15 0.05

DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED

BETWEEN 0.20mm AND 0.30mm FROM THE TERMINAL TIP. IF THE TERMINAL

HAS THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE

DIMENSION b SHOULD NOT BE MEASURED IN THAT RADIUS AREA.

4.76 0.05

9.50 0.05

5

6

COPLANARITY APPLIES TO THE TERMINALS AND ALL OTHER SURFACE

METALLIZATION

1.50 REF

DRAWING SHOWN ARE FOR ILLUSTRATION ONLY

SYMBOL TOLERANCE

aaa

bbb

ccc

0.15

0.10

4.27 0.05

2.25 0.05

0.40 0.05

PACKAGE

OUTLINE

1.35

0.05

0.25 0.05

1.78

REF

RECOMMENDED SOLDER PAD LAYOUT

TOP VIEW

3613fa

34

LTC3613

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

0ꢀ/12 Clarified Electrical Characteristics

Clarified PIn Functions

3, 4

8

Modified Application Circuit

33

3613fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

35

LTC3613

TYPICAL APPLICATION

High Frequency 5V, 4A, 1MHz Step-Down Converter

PV

SV

IN

Efficiency

R

PGD

VIN

INTV

CC

100k

2.2Ω

100

90

80

ꢀ0

60

50

40

30

20

10

0

V

IN

PGOOD

MODE/PLLIN

ꢀV TO 24V

C

+

IN2

C

4ꢀμF

35V

VIN

IN1

4.ꢀμF

0.1μF

R

DIV1

×2

PULSE-

SKIPPING

MODE

0Ω

V

RNG

EXTV

V

CC

R

10Ω

F2

RUN

FORCED

OUT

–

CONTINUOUS

MODE

SENSE

C

SS

0.1μF

C

R

F1

F

1000pF 10Ω

+

SENSE

TRACK/SS

L1

1.2μH

R

SENSE

10mΩ

C

V

5V

4A

ITH1

OUT

R

LTC3613

220pF

SW

ITH

20k

C

B

V

= 12V

OUT

ITH

0.1μF

IN

= 5V

BOOST

R

T

C

R

FB2

14ꢀk

FF

0.01

10

0.10

1

40.2k

D

B

22pF

C

OUT1

RT

LOAD CURRENT (A)

INTV

CC

INTV

CC

22μF

C

VCC

3613 TA11

R

×2

SGND

FB1

4.ꢀμF

20k

PGND

+

V

OSNS

–

3613 TA10

C

: KEMET T521X4ꢀ6M035ATE0ꢀ0

L1: WÜRTH ꢀ44313120

IN1

D : DIODES, INC. SDM10K45

B

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IN

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ꢀmm × 8mm QFN-52 Package

24V, 12A (I ), 1MHz, Synchronous Step-Down DC/DC 957 Efficiency, V : 4V to 24V, V

= 0.6V, I = 900μA, I <15μA,

Q SD

OUT

IN

Converter

9mm × 9mm QFN-64 Package

32V, 10A (I ), 1MHz, Synchronous Step-Down DC/DC 957 Efficiency, V : 4V to 32V, V

= 0.6V, I = 900μA, I <15μA,

Q SD

OUT

IN

Converter

9mm × 9mm QFN-64 Package

LTC3414/

LTC3416

4A (I ), 4MHz, Synchronous Step-Down DC/DC

957 Efficiency, V : 2.25V to 5.5V, V

= 0.8V, I = 64μA, I <1μA,

OUT(MIN) Q SD

OUT

IN

Converter

TSSOP20E Package

LTC3415

ꢀA (I ), 1.5MHz, Synchronous Step-Down DC/DC

957 Efficiency, V : 2.5V to 5.5V, V

= 0.6V, I = 450μA, I <1μA,

OUT(MIN) Q SD

OUT

IN

Converter

5mm × ꢀmm QFN-38 Package

LTC3418

8A (I ), 4MHz, Synchronous Step-Down DC/DC

957 Efficiency, V : 2.25V to 5.5V, V

= 0.8V, I = 380μA, I <1μA,

OUT(MIN) Q SD

OUT

IN

Converter

5mm × ꢀmm QFN-38 Package

LTM4600HV

LTM4601HV

LTM4602HV

LTM4603HV

10A Complete Switch Mode Power Supply

927 Efﬁciency, V : 4.5V to 28V, V : 0.6V, True Current Mode Control,

IN

OUT

Ultrafast Transient Response

12A Complete Switch Mode Power Supply

6A Complete Switch Mode Power Supply

927 Efﬁciency, V : 4.5V to 28V, V : 0.6V, True Current Mode Control,

IN

OUT

Ultrafast Transient Response

927 Efficiency, V : 4.5V to 28V, V : 0.6V, True Current Mode Control,

IN

OUT

Ultrafast Transient Response

937 Efficiency, V : 4.5V to 28V, with PLL, Output Tracking and Margining

IN

3613fa

LT 0712 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-ꢀ41ꢀ

36

●

(408) 432-1900 FAX: (408) 434-050ꢀ www.linear.com


型号：	LTC3608
厂家：	Linear Systems
描述：	24V, 15A Monolithic Step Down Regulator with Differential Output Sensing 24V ， 15A单片式降压稳压器，带有差分输出检测稳压器
文件：	总36页 (文件大小：435K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3608 [Linear Systems]

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